Powerchip Semiconductor Corporation (PSC), a wafer foundry, revealed during its recent earnings conference call that the 1P process developed in collaboration with Micron has entered the development stage. New equipment is expected to be moved in during the first quarter of 2027, with trial production to be completed in the first half of 2028, followed by mass production in the second half of the year. The number of die per wafer for the 1P process is 2.5 times that of its current main process platform, which will significantly contribute to the future increase in DRAM output value. Additionally, the HBM backend wafer manufacturing (PWF) production line, also in collaboration with Micron, has undergone cleanroom expansion at the Hsinchu plant. Equipment move-in is scheduled for the third quarter of 2026, trial production is expected to begin in the fourth quarter of 2026, and mass production is targeted for the fourth quarter of 2027, with a monthly capacity goal of 20,000 wafers.