Samsung Electronics Files New Patent for HBM Packaging

Samsung Electronics has filed a new patent titled "Semiconductor Package Including Vertically Stacked Plurality of Semiconductor Chips," aiming to resolve reliability issues in High Bandwidth Memory (HBM) packaging. According to the application submitted on the 28th, Samsung utilizes a "deep groove sawing" process to shape the sides of the dummy die stacked at the top of the HBM into a three-tiered stepped curved structure. This approach can effectively mitigate common issues in highly stacked HBM, such as chip delamination, cracking, and warpage.

Additionally, in terms of thermal management, the patent precisely designs the vertical distance between the bottom surface of the bonding insulating layer and the horizontal extension surface to be between 1 and 10 micrometers, maintaining heat transfer efficiency at current levels. It also includes an improved protruding surface structure that minimizes the volume of the molding layer, thereby potentially optimizing the heat transfer path.