SPHBM4 Standard Approved, Breaking the Bottleneck of High HBM Packaging Costs

JEDEC has developed and published the SPHBM4 standard. SPHBM4 is a new JEDEC standard that delivers performance close to HBM4 while using fewer signal pins, standard packaging, and more economical substrates.

Reduction in signal pins will lead to some performance losses, but SPHBM4 mitigates this by increasing the signal speeds fourfold while reducing the number of signal pins to 1/5th. This leads to HBM-level bandwidth while using standard substrates. The connection between the memory and the compute die also changes to 20mm. This increased distance enables better internal thermal management for the package.

Specifically, HBM4 features approximately 2,000 pins with a per-pin data rate of about 11 Gbps, delivering a total bandwidth of 2.8 TBps. In contrast, SPHBM4 reduces the pin count to one-fifth that of the current HBM4 solution (approximately 400 pins) by using standard substrates and reducing reliance on complex packaging, while compensating bandwidth with roughly four times the signal speed (increasing the per-pin data rate to about 44 Gbps).

Additionally, the SPHBM4 DRAM utilizes the same DRAM stacks as the HBM4 DRAM (JESD270-4) with a different buffer die to enable assembly in standard packaging. 

With reduced dependence on expensive, advanced packaging, the application scope of high-performance memory is also expected to expand.