Positron has unveiled its second-generation ASIC design, Asimov. It claims that Asimov, which is deeply optimized for Large Language Model (LLM) inference, is expected to achieve five times the key performance indicators—energy efficiency (tokens per watt) and cost-effectiveness (tokens per dollar)—compared to NVIDIA’s next-generation Rubin architecture. Asimov chip consists of a pair of computing modules, each equipped with a systolic array supporting diverse data formats. Each computing module is connected to 432GB of LPDDR5x memory and can access up to 720GB of KV Cache memory via PCIe 6.0/CXL 3.0. The chip has an overall TDP of 400W, a total memory capacity of 2304GB, and a total memory bandwidth of 2.76TB/s, supporting air cooling. Positron aims to complete the tape-out of Asimov chip by the end of 2026 and begin mass production in early 2027.