Huawei Unveils "Tao ( τ ) Law": Powered by Logic Folding, Aiming for 1.4nm-Equivalent Performance by 2031

Tingbo He, Director of Huawei and President of its Semiconductor Business Department, recently officially unveiled the "Tao ( τ ) Law" for the semiconductor industry during a keynote speech.Unlike Moore's Law, which has long guided the traditional semiconductor industry, the core concept of "Tao Law" is to replace conventional "geometric scaling" with "time scaling." Instead of relying solely on shrinking transistor dimensions to boost performance, it establishes the systematic reduction of the time constant ( τ ) as its primary objective.

Leveraging innovative techniques such as Logic Folding, this new principle is dedicated to continuously compressing signal propagation delays. This allows for a simultaneous leap in both transistor density and electronic system performance, without relying on extreme manufacturing process nodes. According to the technology roadmap presented by Huawei, high-end chips evolved under the "Tao Law" are expected to achieve transistor density equivalent to the 1.4nm process level by 2031.