Samsung HBM4E Yield Reportedly Tops 70%, D1d on Track for November PRA

HBM4E Development Accelerates, Core Yield Metrics Stabilize

Following the February rollout of volume shipments for its 6th-gen HBM4 memory, Samsung Electronics has made significant progress in developing its more advanced HBM4E variant. The firm shipped samples of 12-high HBM4E stacks to key clients by late May and released full technical specifications to the market.

HBM4 will feature in NVIDIA's upcoming "Vera Rubin" AI accelerators slated for launch in the second half of the year, while the higher-performance HBM4E is already slotted for next-gen chips including "Vera Rubin Ultra."

Samsung Electronics CTO and Head of the Semiconductor Research Institute Song Jae-hyuk disclosed details during an internal meeting that HBM4E's reliability test yield has surpassed 70%.

Though still short of the widely recognized 80% benchmark for mature mass-production yields, the figure signals encouraging momentum, especially given HBM4E remains in the development and validation stage, indicating the product is rapidly maturing to meet volume manufacturing criteria and that its development cycle has entered a stable phase.

D1d DRAM Process Moves Forward, Targets November PRA Audit

Song Jae-hyuk also stated that Samsung's 7th-gen sub-10nm DRAM manufacturing process (D1d) has established a technological lead over rivals, with a concrete milestone timeline locked in: the company aims to complete PRA this November.

As the final internal quality gate before mass production ramp, the PRA comprehensively audits yield rates, chip performance, and manufacturing throughput; successful clearance authorizes formal mass production ramp-up.

The D1d process carries far-reaching strategic value beyond standalone DRAM chips. Samsung plans to fully migrate its HBM manufacturing to the D1d node starting with the 8th-gen HBM5 memory series.

Industry analysts widely agree that smooth progress on D1d will deliver significant cascading positive effects: it will not only bolster the competitiveness of Samsung's existing DRAM lineup, but also exert a decisive ripple impact on the performance, cost structure, and supply capacity of all future DRAM and HBM5 products.