Samsung Reportedly Delays Mass Production Plan for CXL 3.1 Memory Modules

According to Korean media and industry sources, Samsung Electronics has decided to postpone the mass production of its CXL 3.1-based memory modules (CMM-D 3.0). This decision is primarily driven by the delayed release of CPUs supporting the CXL 3.1 standard by manufacturers such as Intel and AMD. In the short term, Samsung will continue to maintain the production of its CXL 2.0-based CMM-D 2.0 products.

Under the original schedule, Samsung Electronics planned to commence customer sample production of the CMM-D 3.0 in June of this year, but this timeline has now been pushed back. Industry insiders point out that since the CXL 3.1 ecosystem has not yet been established and market maturity remains low, Samsung has shifted its production focus to ramping up CXL 2.0 production based on current demand. Production of CXL 3.1 in the fourth quarter of this year is expected to be primarily for customer sample testing, with full-scale mass production likely delayed until next year.

CXL (Compute eXpress Link) is an interconnect technology based on the PCIe (PCI Express) interface. CXL 3.1 relies on the PCIe 6.0 interface, while CXL 2.0 is based on PCIe 5.0. Achieving PCIe 6.0 performance requires synchronized support from components such as server CPUs, GPUs, solid-state drives (SSDs), and motherboards. However, most components supporting PCIe 6.0 have not yet been released to the market.

Neither Intel nor AMD has currently launched CPUs supporting PCIe 6.0. Industry analysis suggests that the server industry will only be ready to adopt CXL 3.1 once next-generation server platforms, such as Intel's Diamond Rapids or AMD's EPYC Venice, become available. Intel's Diamond Rapids server CPU, originally slated for release in the second half of this year, has been delayed to the second or third quarter of next year due to design changes and production yield issues. AMD's EPYC Venice is expected to be released in the second half of this year, with engineering samples (ES) already delivered to major vendors. Samsung plans to produce CMM-D 3.1 samples based on the EPYC Venice system after September this year. Following successful customer quality testing, mass production is expected to commence, with industry estimates pointing to the first quarter of next year.

Previously, in October last year at the OCP Summit in the US, Samsung Electronics announced plans to be the first to launch CXL 3.1-compliant CMM-D products in the fourth quarter of 2025. However, as market demand has become highly concentrated on general-purpose DRAM and HBM, attention to the CXL market has waned. Coupled with delays in building the CXL 3.1 ecosystem, these factors ultimately prompted Samsung to adjust its mass production schedule. Currently, SK Hynix and Micron have completed the development of their CXL 3.1 memory modules, but neither has shown clear signs of production readiness.

In terms of technical features, CXL memory supports "memory pooling," which enables flexible memory allocation through switching technology. This breaks the limitations of CPU and GPU memory usage, thereby improving overall system efficiency. Unlike traditional server DRAM modules (RDIMMs) that can only be installed in dedicated slots, CXL memory can flexibly expand capacity via interfaces, much like PC SSDs. However, compared to HBM, CXL memory has lower bandwidth and operating speeds, making the two technologies complementary in practical applications.

In response to the adjustments in its mass production plan, Samsung Electronics stated, "Although some plans have changed, we are continuing to prepare smoothly for the originally scheduled mass production timeline." The industry generally interprets this as Samsung still being on track to achieve mass production readiness for CXL 3.1-related products within the fourth quarter of this year.