TSMC's CoPoS Pilot Line Expected to Be Completed by June, Panel-Level Packaging Mass Production on the Horizon

According to Taiwanese media reports, TSMC's CoPoS (Chip-on-Panel-on-Substrate) pilot production line began equipment delivery in February this year and is expected to be fully completed by June. The line is located at the facility of TSMC's subsidiary Visera, with small-volume trial production scheduled for the second half of 2026.

CoPoS is regarded by the industry as a "panelized" upgrade of TSMC's mainstream CoWoS packaging technology. Taking NVIDIA's Rubin GPU as an example, as AI chips continue to grow in size, its area has reached 5.5 times that of traditional chips. A standard 12-inch wafer can only accommodate seven Rubin chips, and in some cases only four. This has pushed the industry to seek more efficient packaging solutions.

CoPoS replaces the traditional circular silicon interposer with a square panel, significantly improving material utilization. Reports indicate that the technology uses panel sizes of up to 310×310mm, 515×510mm, or even 750×620mm, far larger than a 300mm round wafer. Its long-term goal is to replace the silicon interposer with a glass substrate, thereby breaking through the capacity bottleneck in advanced packaging.

Industry consensus expects that mass production of CoPoS will gradually ramp up between 2028 and 2029. Production will be located at TSMC's Advanced Packaging and Testing 7 Plant (AP7) in Chiayi, with the P4 and P5 sections serving as core hubs. Meanwhile, TSMC has also planned two advanced packaging plants in Arizona, USA, focusing on SoIC and CoPoS technologies respectively, with the first plant scheduled for mass production in 2028.

It is worth noting that supply chain sources have cautioned that as substrate sizes increase, the warpage problem becomes more severe, posing one of the biggest obstacles to mass production. TSMC is currently working with material and equipment supply chains to actively address this challenge. Chiayi is rapidly emerging as a key base for TSMC's advanced packaging, where multiple technologies including CoPoS, SoIC, and WMCM will be integrated to create the largest advanced packaging cluster in TSMC's history.