CXMT Reportedly Accelerates DDR6 Layout, Aiming for World's First Mass Production of LPDDR6 in 2H2026

According to media reports, CXMT is moving early to lay out its DDR6 supply chain, having brought in new packaging substrate and lead frame supplier Haesung DS. The company is also considering switching to panel‑level processes that support multi‑layer designs, replacing the Reel-to-Reel production method used for DDR4 and DDR5, in order to meet the more demanding multi‑layer requirements of DDR6.

It is said that Haesung DS passed CXMT's DDR5 packaging substrate quality tests in the first quarter of this year. Initial shipments are expected to start contributing to revenue in the second quarter, with supply volumes scaling up significantly by 2027. For the DDR6 phase, Haesung DS is expected to adopt new panel‑level processes to help maintain production efficiency and avoid technical bottlenecks.

In terms of the progress, CXMT's LPDDR6 chips have already entered the sampling phase. In theory, the existing Reel-to-Reel process could also be used for DDR6 manufacturing. However, as the number of circuit layers increases, both profitability and production efficiency would decline, making panel‑level processes a more robust choice. CXMT is pushing ahead with panel‑level production methods to prepare for DDR6 mass production in advance. The report states that CXMT's LPDDR6 is expected to achieve the world's first mass production in the second half of 2026, with the speed of 12.8 Gbps, directly competing with flagship products from Samsung and SK hynix.